1. Field of the Invention
The present invention relates to the field of displaying, and in particular to a method for manufacturing a high resolution AMOLED (Active Matrix Organic Light Emitting Diode) backplane.
2. The Related Arts
Compared to a TFT-LCD (Thin-Film Transistor Liquid Crystal Display), which is the current main-stream display technology, an OLED (Organic Light-Emitting Diode) display device has a variety of advantages, such as wide view angle, high brightness, high contrast, low power consumption, and being more compact and lighter and is an attention-attracting spot of current flat panel displaying technology. Driving of the OLED display devices is classified in two types, namely passive matrix (PM) and active matrix (AM). Compared to the passive matrix driving, the active matrix driving possesses advantages, such as large quantity of displayed message, low power consumption, extended device lifespan, and high image contrast.
The conventional active matrix organic light emitting diode (AMOLED) display devices use, primarily, low temperature poly-silicon thin-film transistors (LTPS-TFTs) to drive the OLED to give off light. Generally, an AMOLED display device essentially comprises a switch TFT, a driving TFT, a storage capacitor (Cst), and an OLED. In a regular AMOLED display device, the storage capacitor stores a data signal that is switched by the switch TFT and, in response to the data signal stored therein, drives the driving TFT so as to uses an output current that corresponds to the data signal to make the OLED emitting light.
As shown in FIG. 1, a schematic view is given to illustrate a structure of a low temperature poly-silicon array (LTPS-array) of a conventional AMOLED backplane. A manufacturing process of the AMOLED backplane is as follows: depositing a first buffer layer 101 and a second buffer layer 102 on a substrate 100, wherein the first buffer layer 101 can be SiNx and the second buffer layer 102 can be SiOx; depositing an amorphous silicon (a-Si) layer on the second buffer layer 102, followed by a high-temperature dehydrogenation process to remove the hydrogen content of the a-Si layer and a low-temperature poly-silicon process to convert the a-Si layer into a low temperature poly-silicone (Poly-Si) layer, and patternizing of the low temperature poly-silicon layer to form a patternized low temperature poly-silicon layer 10; subjecting the patternized low temperature poly-silicon layer 110 to a P+ ion doping process by injecting P+ ions; depositing a gate insulation (GI) layer 111 on the patternized low temperature poly-silicon layer 110; depositing a gate terminal metal layer on the gate insulation layer 111 and applying a masking operation to the gate terminal metal layer for exposure, followed by development and etching operations to form a gate terminal 120; depositing a first insulation layer 121 and a second insulation layer 122 on the gate terminal 120, and using contact windows to make source/drain terminals 130 by, followed by formations of a planarization layer (PL) 140, an electrode layer 150, a bank 160, and spacers (PS) 170.
Patternization of the poly-silicon layer or other layers is achieved with a yellow light process, of which a specific way of performance is: covering a layer of photo-sensitive material on the poly-silicon layer, the layer being referred to as a photoresist layer, and then allowing light to pass through a mask to irradiate the photoresist to cause exposure of the photoresist. Since the mask carries a pattern of the poly-silicon layer, a portion of the light is allowed to pass through the mask to irradiate the photoresist layer, whereby the exposure of photoresist layer is done in a selective way, and it helps to completely duplicate the pattern of the mask on the photoresist. Then, a proper developer is applied to remove a portion of the photoresist so as to have the photoresist layer presenting a desired pattern. Then, an etching operation is applied to remove residual poly-silicon layer, wherein the etching operation can be selected from wet etching, dry etching, and a combination thereof. Finally, the remaining patternized photoresist layer is completely removed to complete the patternization process of the poly-silicon layer.
In FIG. 1, as well as other drawings of the present invention, the texts of “switch TFT”, “driving TFT”, and “storage capacitor” respectively and generally indicate the locations of the corresponding structure of the switch TFT, driving TFT, and storage capacitor in the drawings. The patternized poly-silicon layer 110 formed through patternization of the low temperature poly-silicon layer generally comprises a storage capacitor area 1, TFT source/drain areas and channels 2, 3. The storage capacitor area 1 is provided for the formation of a storage capacitor. The TFT source/drain area and channel 2 is provided for the formation of the source/drain terminals and the channel of a switch TFT. The TFT source/drain area and channel 3 is provided for the formation of the source/drain terminals and the channel of a driving TFT. As shown in FIG. 1, in the prior art technology, the buffer layers and the amorphous silicon layer are deposited first and then the amorphous silicon is subjected laser-driving crystallization to become a low temperature poly-silicon layer, followed by patternization through yellow light and etching operations. The low temperature poly-silicon layer is subjected to a doping operation. The other layers are respectively formed through deposition/yellow light/etching operations. Since a storage capacitor is to be formed, doping of P+ must be done before the gate terminal 120 is formed. In order to avoid shifting of yellow light, the switch TFT and the driving TFT are made as gate overlap TFTs with a single-side overlapping length L being at least 1.25 micrometers. Due to the necessity of increasing the width of the gate terminal, the light transmittance of the panel is influenced, making it disadvantageous for increasing the resolution of the panel.